![]() ![]() To integrate a USRP X3X0 into your C++ application, you would generate a UHD device in the same way you would for any other USRP:Īuto usrp = uhd::usrp::multi_usrp::make( "type=x300") įor a list of which arguments can be passed into make(), see Section Device arguments. Like any other USRP, all X3X0 USRPs are controlled by the UHD software. There should be no more warnings at this point, and all components should be correctly detected. When your FPGA is up to date, power-cycle the device and re-run uhd_usrp_probe. See Load the Images onto the On-board Flash for more details. Make sure the process of flashing the image does not get interrupted. The process of updating the FPGA image will take several minutes. If you have installed the images to a non-standard location, you might need to run (change the filename according to your device): uhd_image_loader -args="type=x300,addr=192.168.10.2" -fpga-path="/usrp_x310_fpga_HG.bit" Use the uhd_image_loader utility to update the FPGA image. You can use the uhd_images_downloader script provided with UHD (see also Firmware and FPGA Images). However, if there were errors regarding the FPGA version compatibility number, you will have to update the FPGA image before you can start using your USRP. If the output from uhd_find_devices and uhd_usrp_probe didn't show any warnings, you can skip this step. To make sure all of your components (daughterboards, GPSDO) are correctly detected and usable. At this point, you should also run: uhd_usrp_probe -args addr=192.168.10.2 You will also be able to ping the USRP by running: ping 192.168.10.2 If your network configuration is correct, running uhd_find_devices will find your USRP and print some information about it. Note: If you are running an automatic IP configuration service such as Network Manager, make sure it is either deactivated or configured to not change the network device! This can, in extreme cases, lead to you bricking the USRP! See Setup the host interface on details how to change your machine's IP address. It is recommended to directly connect your USRP to the computer at first, and to set the IP address on your machine to 192.168.10.1. An otherwise unconfigured USRP device will have the IP address 192.168.10.2 when using 1GigE. The next step is to make sure your computer can talk to the USRP. Connect the power supply and switch on the USRP.Connect the 1 GigE SFP+ transceiver into the Ethernet port 0 and connect the X300/X310 with your computer.Note that you will need an external GPS antenna connected to the rear GPS ANT connector in order to make use of GPS, although your USRP will still be usable without. If you have purchased an internal GPSDO, follow the instructions on Internal GPSDO Application Notes (USRP-X3x0 Models) to insert the GPSDO.In order to avoid confusion, make sure the internal connections match the labels on the front panel (i.e. Connect the RF connectors on the daughterboards to the front panel.Insert the daughterboards by inserting them into the slots and optionally screwing them onto the motherboard.Unscrew the top of your X300/X310 (there are 2 screws which can be easily loosened using a small Phillips screwdriver).by touching a radiator) in order not to damage sensitive electronics through static discharge! For 10 Gigabit Ethernet (10GigE) or PCI Express (PCIe), see the corresponding sections in this manual page.īefore you can start using your USRP, you might have to assemble the hardware, if this has not yet happened. Here, we assume you will connect your USRP using Gigabit Ethernet (1GigE), as this interface is readily available in most computers. This will run you through the first steps relevant to get your USRP X300/X310 up and running. Up to 120 MHz of RF bandwidth with 16-bit samples.External USB Connection for built-in JTAG debugger.External GPIO Connector with UHD API control.Supported master clock rates: 200 MHz and 184.32 MHz.External reference (10 MHz, 11.52 MHz, 23.04 MHz, or 30.72 MHz) input & output. ![]() Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE).2 transceiver card slots (can do 2x2 MIMO out of the box).NI RIO Kernel Modules for X-Series PCIe Connectivity.System Configuration for USRP X3x0 Series.Internal GPSDO Application Notes (USRP-X3x0 Models).Configuring the device in an application.Debugging custom FPGA designs with Xilinx Chipscope.Device not enumerated over PCI-Express (Windows).Device not enumerated over PCI-Express (Linux).Load the Images onto the On-board Flash. ![]()
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